1. Field of the Invention
This invention relates generally to dielectric structures, and more particularly to dielectric structures for dual-damascene applications.
2. Description of the Related Art
Semiconductor devices are made from multi-layer structures that are fabricated on semiconductor wafers. Of great importance to the multi-layer structures is the dielectric materials used in between metallization interconnect lines. In dual-damascene applications, the metallization interconnect lines are defined in trenches that are etched into dielectric layers. Typically, the interconnect metallization is a copper (Cu) material, and the conductive vias are also integrally formed of Cu. As is known to those skilled in the art, there are three general techniques for fabricating metallization interconnect lines and conductive vias. The techniques include: (i) a via first fabrication; (ii) self-aligned fabrication; and (iii) trench first fabrication.
As the demand for faster device speeds continue to increase, fabrication and design engineers have been implementing lower dielectric constant materials. Typically, the speed of an interconnect structure is characterized in terms of RC (resistance/capacitance) delays. Lower dielectric constant materials help in reducing inter-metal capacitance, and therefore, results in reduced delays and faster devices.
The move toward lower dielectric materials has included the use of both organic as well as inorganic materials. One type of lower dielectric material includes a carbon doped silicon dioxide (C-oxide). C-oxide typically has a dielectric constant of about 3.0 or lower, compared to dielectric constants of about 4.1 for silicon dioxides (e.g., un-doped TEOS). Although lower dielectric constants are achieved using C-oxide, this type of inorganic material poses etching difficulties. These difficulties are primarily due to the fact that C-oxide is partially organic (i.e., due to the carbon) and partially inorganic (i.e., silicon dioxide). Also, etch chemistries are generally optimized for inorganic only or organic only films.
To further describe these difficulties, reference is now made to FIG. 1. As shown, a dielectric 10 is shown having a copper trench line 12 with a liner barrier 14. A barrier layer 16a is used to prevent copper from diffusing into the dielectric 10. A first oxide layer 18a is deposited over the barrier layer 16a, and a trench stopping layer 16b is deposited over the first oxide layer 18a. A second oxide layer 18b is then deposited over the trench stopping layer 16b. In cases where the first and second oxide layers 18a and 18b are un-doped TEOS oxide or fluorine doped oxides, there are well developed etching techniques that provide excellent selectivities to the layers 16a and 16b. For example, such selectivities are in the range of about 20:1, which therefore enable the thicknesses of the layers 16a and 16b to be kept at a minimum. This is important because layers 16, which are typically made of silicon nitride (SiN) or silicon carbide (SiC) have dielectric constant levels as high as about 9. Selectivities in the 20:1 range therefore prevent the barrier layer 16a from being prematurely removed when relatively thin layers are formed.
On the other hand, when lower dielectrics such as C-oxide are implemented for oxide layers 18a and 18b, the selectivity to the barrier layers 16 is reduced to ranges nearing about 5:1. This reduction in selectivity therefore causes the barrier layer 16a to be removed at location 30, thereby exposing the underlying copper line 12 to oxygen. When this happens, increased oxidation of the exposed copper will occur (during ashing operations and the like), which therefore generates higher resistive contacts through via holes 20. Even though the barrier layer 16a will be removed prior to sputtering with a liner barrier, the premature exposure does increase the degree of oxidation. In addition, once the copper is exposed, an amount of copper can be etched and possibly caused to be deposited into the dielectric walls of the via holes 20. Obviously, if copper material were to be deposited into the inter-metal dielectric, a device may fail to optimally perform in accordance with desired performance specifications.
In view of the foregoing, there is a need for low K dielectric materials for use in dual-damascene applications that etch well and retain high selectivity to copper barrier layer materials.